There's no sense to convert addresses. I can imagine this done as "virtual machine", with interpreter of 6502 codes, where FPGA would be helpful but wouldn't do all the stuff. Since there's no 1:1 size nor 1:1 speed match, we need to emulate a lot of "specific" functions of 6502 with "generic" functions of '51.
So:
- We keep basic original '51 registers strictly for our own program purposes. Our great profit is that 6502 has way less registers than '51. We need PC,A,X,Y,F and SP in 7 bytes, R1-R7 perfectly enough (leave R0 for our own purposes, bank switching only when necessary. Eventually map F onto something rarely used bit addressable, i.e. B or 20h, DPTR would be nice for PC but you still need to access the stack, R1 for SP?)
- We use XRAM as the program+data 6502 memory, internal code as the emulator software memory.

The FPGA would be useful for
- exception table (when to read/write RAM, when to perform SFR operation)
- recognizing and signalling interrupts (which from our '51 side wouldn't be interrupts really, just external signals to branch the program into interrupt routine)
- Possibly calculate routine addresses? Decode the 6502 instruction, but instead of converting it to '51 opcode, set '51 port values, so 51 does the following:
PUSH P0
PUSH P1
RET
and RET brings the program to routine that services given event - command, interrupt, reset, init...