As a '51 device performs as the central processor;

1) Does the '51 retain it's Harvard Architecture?

The "CPU" '51 - no. It uses external RAM for both data and program to allow more flexiblity (loading, editing, relocating software "on the fly"). The "peripherials" use Harvard architecture, utilizing internal flash for "firmware", eventually temporarily giving it up when they work as "generic coprocessors" and reading program from XRAM.

2) Will i/o interconnect within the Data MAP or connect to processor pin's?

All general purpose I/O will connect to the "external" I/O '51 chip. Whether the chip itself is memory mapped or connected by some other means, is still open.

3) Will "mass store" (IDE or otherwise) be intimate or a co-processor?

Mass Storage together with all other I/O will be accessed through a dedicated chip.

3a) If "mass store" is not intimate is it a "channel" interface requiring central processor intervention for data to propagate to memory or does it "DMA".

Both modes available, read byte-by-byte by processor on request or transfer a block of data to location of memory or flush it back to disk.

4) If video is not intimate to the central processor, (which seems to be the prevalent opinion) is it a channel device or does it share the Data Memory map?

4a) it is, because it would eat up 98% of CPU time otherwise.
I'd definitely prefer a separate Video RAM, i.e. dual port chip.

5) How much of the "OS" exist's prior to boot load from "mass storage".

All. I suggest placing it in Flash of the CPU chip, so it loads all from internal memory and upon execution of a user program the CPU switches to external memory.