In the interest of continuing and stimulating discussion, I propose the following internal bus for the 8052 computer. I'm open to corrections, critiques, suggestions, or completely alternative ideas. I don't doubt that there are others here that can come up with a better solution.



DB0-DB7: Byte-wide parallel data bus.

SEL_*: There would be one select line for each of the 3 slaves. A slave would be selected when its corresponding select line is high. A slave would drive this line low if it is busy and must ask the central 8052 to wait.

CLK_OUT: Normally high, but brought low by the central 8052 when it has placed data on the data bus to be clocked out to the selected slave. The slave's select line could be NANDed with the CLK_OUT line to produce a 1-0 transition when the slave is selected and there is a byte waiting. This could trigger an external interrupt on the slave 8052 which would immediately process the byte on the data bus.

RD_WR: Central 8052 would maintain this line high when it is attempting to read from a slave 8052 and would bring this line low when attempting to write to a slave 8052. When high (reading from slave 8052), the slave 8052 would pull this line low to clock out a byte on the data bus.

ACK: This line would normally be high and would be pulled low by an 8052 to acknowledge a byte has been received. In the case of a slave this line would be pulled low until the central 8052 brings the CLK_OUT line high again. In the case of the central 8052 (after reading data from a slave) this line would be pulled low until the slave stops pulling RD_WR low.

Any thoughts? Alternative ideas?

Regards,
Craig Steiner