I have done a lot of interprocessor communication, the real issue is synchronization. If the master can not depend on an immediate response from any slave, it will spend most of its time waiting for slaves to get ready. I tried master request, go away and request again a bit later making the slave get ready to respond ready, that tend to stall the slaves.

If you implement the "slave holding the line low means busy" technique and make that work without performance attrition, I will be surprised, I have tried many ways, but with no success.

Anyhow all schemes I have used with any success are based on communicating via ISR driver. I have found that using chips with hardware IIC I can achieve a "communication does not slow the process down" operation. Parallel I have achieved it by the communications control lines being interrupts at the receiving end and this can be achieved by using the "lots of interrupt sources" chips. E. g. a comparator input that generate an interrupt acn be used just as well as a logical interrupt source.

There is one more possibility that I thought of, but never implemented which would be a shared CPLD. The system was that any device could write a byte and set a flag, when the recepient got around to reading the byte, it would clear the flag.

Erik