??? 09/21/04 02:03 Read: times |
#77760 - RE: Phillip video user page Responding to: ???'s previous message |
Craig,
An SiLabs eval board would be nice platform especially if it had a lot of XRAM (>8kB). The image created is stricking due to the repeating pattern. This repetition is due to looping 1kB of XRAM internal to the DS'420, 4.5 times. Also it's a composite of test routines that:
CPU time is completely dominated by the Video Display. Video timing has to be deterministic so you code "equal path lengths" from any conditional. No interrupts. Vertical Retrace is where you service other purposes than video. Using a DS'420 class processor, there is enough space in the Horizonal Sync pulse time to check for waiting data and to insert into a FIFO. So every 63.5 usec's you can service Input, here a serial port @ approx 19.2kBPS is intended. The 68 "off the screen" blank lines that surround Vertical Synch, are a good place to translate incoming characters to screen font or commands into video operations. regards, p |