Hi All,

Actually 64, but for the time being, Thirty two HC573s are supposed to be placed at addresses FFE0H..FFFFH and be written to by MOVX instruction, AND The rest of the address space (0000H..FFDFH) is used by a 28F512. Briefly an I/O expansion is needed. I know...I know I2C parts like PCF8574 are already invented, but when it comes to 32 and especially 64 8-bit I/Os (actually just Os) considering the 2 lines needed for every 8 ports (Okay every 16 ports) we shall need 4 or 8 lines, on the other hand, placing HC573s on P0 virtually consummes no pin. So at least for the time being, lets forget about I2C. Back to the HC573 solution. The decoder needed for 28F512 (0000H..FFD0H) is this:

Every thing sounds fine with it, but the best decoder I could design for the /LE of the 32 HC573s is this:

Now the problems with this decoder are:
- large chip count.
- I'm badly worrying about the propagation delay through all these stages that may provide the /LE signals too late.
- I'm badly worrying about the "glitches" that may be produced by this scheme.
- /WR is to be connected to 32 or 64 gates. The fan out problem?(Althogh the NOR gates are HCs.)
What would you do if you wanted to have 32 or 64 8-bit outputs?

Best.