And I am bored of this now here is some VHDL I knocked together which implements the basic idea just using 8 registers but you can edit it to work with more,and it just saves a load of arsing about with propagation delays.Only trouble is all my formatting has dropped off,boo hoo!




library ieee;
use ieee.std_logic_1164.all;
use Ieee.numeric_std.all;
entity decoder is

port( clk :in std_Logic;
nRst :in std_logic;
addr_data:in unsigned(7 downto 0);
addr_high:in unsigned(7 downto 0);
ale :in std_logic;
nPsen :in std_logic;
nRd :in std_logic;
nWr :in std_logic;
flash_cs :out std_logic;
latch_o_0 :out unsigned(7 downto 0);
latch_o_1 :out unsigned(7 downto 0);
latch_o_2 :out unsigned(7 downto 0);
latch_o_3 :out unsigned(7 downto 0);
latch_o_4 :out unsigned(7 downto 0);
latch_o_5 :out unsigned(7 downto 0);
latch_o_6 :out unsigned(7 downto 0);
latch_o_7 :out unsigned(7 downto 0));
attribute enum_encoding : string;
end decoder;

architecture rtl of decoder is
constant upper_addr : unsigned :="11111111"; --- upper byte of address
constant bit_mask : unsigned :="00011111";
type UC_STATE_TYPE is (IDLE, ADDR_DECODE,ADDR_MATCH, DATA_TRS, END_CYCLE);
attribute enum_encoding of UC_STATE_TYPE: type is "00001 00010 00100 01000 10000";
signal prs_state, next_state : UC_STATE_TYPE;
signal latch_addr,latch_data :unsigned(7 downto 0);

begin

dec: process(nRst,clk,latch_addr,latch_data)
begin
if nrst='0' then
latch_o_0<=(others=>'0');
latch_o_1<=(others=>'0');
latch_o_2<=(others=>'0');
latch_o_3<=(others=>'0');
latch_o_4<=(others=>'0');
latch_o_5<=(others=>'0');
latch_o_6<=(others=>'0');
latch_o_7<=(others=>'0');
elsif rising_edge(clk) then
case latch_addr is
when "00000000" => latch_o_0 <= latch_data;
when "00000001" => latch_o_1 <= latch_data;
when "00000010" => latch_o_2 <= latch_data;
when "00000011" => latch_o_3 <= latch_data;
when "00000100" => latch_o_4 <= latch_data;
when "00000101" => latch_o_5 <= latch_data;
when "00000110" => latch_o_6 <= latch_data;
when "00000111" => latch_o_7 <= latch_data;
when others => null;
end case;
end if;
end process;

UC_SM_REGS: process ( nRst,clk)
begin
if nRst = '0' then
prs_state <= IDLE;

elsif rising_edge(clk) then
prs_state <= next_state;
if ((prs_state=addr_match) or (prs_state=data_trs)) then
flash_cs<='1';
else
flash_cs<='0';
end if;
end if;

end process;

Uc_decode: process (prs_state,ale,nRd,nWr,nPsen,addr_data,addr_high )

begin


case prs_state is
when IDLE =>

if ale='1' and nPsen = '1' then
next_state <= ADDR_DECODE;
end if;



when ADDR_DECODE =>
if (addr_high=upper_addr and addr_data > x"DF" ) then
next_state<=addr_match;
else next_state <=idle;
end if;

when ADDR_MATCH =>

if nWr='1' then
latch_addr<=addr_data and bit_mask;

else
latch_data <= addr_data;
next_state <= data_trs;
end if;

when DATA_TRS =>


if nRd = '1' and nWr = '1' then
next_state <= END_CYCLE;
end if;



when END_CYCLE =>


if ale = '0' then
next_state <= IDLE;
end if;


end case;

end process;

end rtl;
























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