| ??? 01/21/05 20:15 Read: times |
#85531 - synchronicity Responding to: ???'s previous message |
Jan Waclawek said:
Isn't it a problem a bit, that there is usually an undefined skew between the '51 input clock and the output signals (ALE, PSEN, A/D)? Yes, you are correct. Use ALE as a latch enable; modern FPGA and CPLD families can configure the flip-flops into transparent latches (although you must be sure!). You can use a clock local to the FPGA and synchronize the data and latched address to it in the usual way (two flops in series). In the past, I've used things like 40 MHz clocks, which are fast enough to essentially "oversample" the 8051 signals, but not blazing fast such that layout or meeting FPGA/CPLD timing are issues. It's all a matter of making sure you meet the timing specs. -a |
