I think what Erik wanted to say is, that with decoupling capacitors with each chip the signal return currents need not necessarily to flow over the common Vcc routing of PCB.
Even with ferrites in the individual Vcc lines to each chip this will not have any influence. But it will obviously with ferrites in the ground lines!

Or by other words: When having proper decoupling measures with each chip, common Vcc routing of PCB need not necessarily to be part of signal path, but only Vcc pins. Decoupling capacitors prevent signal return currents from flowing over the common Vcc routing of PCB.

For me situation looks like the following. When output of CMOS gate goes high, a charging of stray capacitance, here represented by 'Cstray', will occur. As consequence decoupling capacitor CX1 is discharged, while 'Cstray' is charged. A ground return current will flow across the ground plane between both chips:



When the output goes low again, the formerly charged stray capacitance 'Cstray' will be discharged again. Again a ground return current will flow across the ground plane between both chips, but now in opposite direction:



By the way, the same is valid, if more stray capacitances are assumed to be present, means from output to Vcc pin, from output to ground pin and from input to Vcc pin. In all these cases, all the charging and discharging currents need not necessarily to flow along the common Vcc routing of PCB, but can also flow entirely through the decoupling capacitors.

The above makes clear, how important good power supply decoupling measures are, and how important it is to have a solid ground plane...

Kai